- Embedded system design for cognitive/intelligent radio application;
- High-efficiency computer architectures for deep learning;
- Optimization techniques for high-performance computing architecture design;
- Hardware accelerators for network security and next-generation SDN-enabled networking;
- Application-specific microprocessor architectures and ASIPs.
Functions and biography
Shervin Vakili has joined Énergie Matériaux Télécommunications Research Centre at Institut National de la Recherche Scientifique (INRS-EMT) as an assistant professor in Feb. 2022. He received his Ph.D. degree in computer engineering from Polytechnique Montréal, Montreal, Canada, in 2014. After Ph.D., he pursued his research in computer architecture as a post-doctoral fellow, a research associate and a professional researcher at Polytechnique Montréal and École de Technologie Supérieure, Montréal, Canada, for more than five years. He has extensive research experience in ASIC- and FPGA-based computer architecture design for applications in artificial intelligence, telecommunication and computer networks.
His research interests include high-efficiency computer architectures, real-time embedded systems and edge computing.
M. Ahmadi, S. Vakili and J. M. P. Langlois, “CARLA: a convolution accelerator with a reconfigurable and low-energy architecture,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
S. Vakili, J. M. P. Langlois, and Y. Savaria, “Enhanced Bloom filter utilisation scheme for string matching using a splitting approach,” IET Communications, vol. 12, 2018.
S. Vakili, J. M. P. Langlois, and G. Bois, “Accuracy-aware processor customization for fixed-point applications,” IET Computers & Digital Techniques, vol. 10, 2016.
S. Vakili, J. M. P. Langlois, and G. Bois, “Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 1853-1865, 2013.
S. Vakili, J. M. P. Langlois, and G. Bois, “Customised soft processor design: a compromise between architecture description languages and parameterisable processors,” IET Computers & Digital Techniques, vol. 7, 2013.
S. Vakili, S. M. Fakhraie, and S. Mohammadi, “EvoMP: a novel MPSoC architecture with evolvable task decompo¬sition and scheduling,” IET Computers & Digital Techniques, vol. 4, no. 2, Mar. 2010.
A. Farmahini-Farahani, S. Vakili, S. M. Fakhraie, S. Safari, and C. Lucas, “Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization,” Elsevier J. of Engineering Applications of Artificial Intelligence, vol. 23, no. 2, pp. 177-187, Mar. 2010.
M. Ahmadi, S. Vakili, J. M. P. Langlois, “An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs,” in IEEE International NEWCAS Conference (best paper award), 2020.
M. Ahmadi, S. Vakili, J. M. P. Langlois, “Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators,” in IEEE International NEWCAS Conference, 2020.
M. Ahmadi, S. Vakili and J. M. P Langlois, “Power reduction in CNN pooling layers with a preliminary partial computation strategy,” in IEEE International NEWCAS Conference, 2018.
I. Sarbishei, S. Vakili, J. M. P. Langlois, and Y. Savaria, “Scalable memory-less architecture for string matching with FPGAs,” in Symposium on Circuits and Systems (ISCAS), May 2017.
S. Vakili, J. M. P. Langlois, B. Boughzala and Y. Savaria, “Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm,” in ACM/IEEE Symp. Architectures for Networking and Communications Systems (ANCS’2015), March 2016.
S. Vakili, J. M. P. Langlois, and G. Bois, “Finite-precision error modeling using affine arithmetic,” in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Vancouver, May. 2013, pp. 2591-2595.
S. Vakili, D. C. Gil, J. M. P. Langlois, Y. Savaria, and G. Bois, “Customized embedded processor design for global photographic tone mapping,” in 18th IEEE International Conference on Electronics, Circuits and Systems, Beirut, Lebanon, Dec. 2011, pp. 382–385.
S. Vakili, S. M. Fakhraie, and S. Mohammadi, “Designing an MPSoC architecture with run-time and evolvable task decomposition and scheduling,” in 5’th IEEE Intl. Conf. Innovations in Information Technology, Dubai, Dec. 2008.
S. Vakili, S. M. Fakhraie, S. Mohammadi, and A. Ahmadi, “Particle swarm optimization for run-time task decomposition and scheduling in evolvable MPSoC,” in IEEE. Intl. conf. Computer Engineering and Technology, Singapore, Jan. 2009